`timescale 1ps/1ps

module test_tb (
    
);

reg clk,rstn;
wire [15:0] sign;

initial begin
    clk = 0;
    forever begin
        #5 clk = ~clk;
    end
end

initial begin
    rstn = 1;
    #1 rstn = 0;
    #5 rstn = 1;
end

test u_test(
    .clk  (clk  ),
    .rstn (rstn ),
    .sign (sign )
);

    
endmodule